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Instruction and logic for optimization level aware branch prediction |
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| 10101999 |
Memory address collision detection of ordered parallel threads with bloom filters |
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2018-10-16 |
| 10013326 |
Propagating a prefetching profile bit from a prefetch queue to a data cache to indicate that a line was prefetched in response to an instruction within a code region |
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Exploiting frame to frame coherency in a sort-middle architecture |
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Exploiting frame to frame coherency in a sort-middle architecture |
Juan Fernandez, Javier Carretero Casado, Tomas G. Akenine-Moller |
2018-03-20 |
| 9904977 |
Exploiting frame to frame coherency in a sort-middle architecture |
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2018-02-27 |