MA

Mohammad Abdallah

IN Intel: 19 patents #47 of 5,158Top 1%
Overall (2018): #1,634 of 503,207Top 1%
19
Patents 2018

Issued Patents 2018

Patent #TitleCo-InventorsDate
10146548 Method for populating a source view data structure by using register template snapshots 2018-12-04
10140138 Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation Ankur Groen, Erika Gunadi, Mandeep Singh, Ravishankar Rao 2018-11-27
10083041 Instruction sequence buffer to enhance branch prediction efficiency 2018-09-25
10048964 Disambiguation-free out of order load store queue 2018-08-14
10031784 Interconnect system to support the execution of instruction sequences by a plurality of partitionable engines 2018-07-24
10019263 Reordered speculative instruction sequences with a disambiguation-free out of order load store queue 2018-07-10
9990198 Instruction definition to implement load store reordering and optimization Gregory A. Woods 2018-06-05
9965277 Virtual load store queue having a dynamic dispatch window with a unified structure 2018-05-08
9946538 Method and apparatus for providing hardware support for self-modifying code Karthikeyan Avudaiyappan 2018-04-17
9940134 Decentralized allocation of resources and interconnect structures to support the execution of instruction sequences by a plurality of engines 2018-04-10
9928121 Method and system for implementing recovery from speculative forwarding miss-predictions/errors resulting from load store reordering and optimization 2018-03-27
9928179 Cache replacement policy Karthikeyan Avudaiyappan 2018-03-27
9921842 Guest instruction block with near branching and far branching sequence construction to native instruction block 2018-03-20
9904625 Methods, systems and apparatus for predicting the way of a set associative cache Ravishankar Rao, Karthikeyan Avudaiyappan 2018-02-27
9904552 Virtual load store queue having a dynamic dispatch window with a distributed structure 2018-02-27
9898412 Methods, systems and apparatus for predicting the way of a set associative cache Ravishankar Rao, Karthikeyan Avudaiyappan 2018-02-20
9891924 Method for implementing a reduced size register view data structure in a microprocessor 2018-02-13
9886279 Method for populating and instruction view data structure by using register template snapshots 2018-02-06
9858206 Systems and methods for flushing a cache with modified data Karthikeyan Avudaiyappan 2018-01-02