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Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation |
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Instruction sequence buffer to enhance branch prediction efficiency |
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Disambiguation-free out of order load store queue |
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Interconnect system to support the execution of instruction sequences by a plurality of partitionable engines |
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Reordered speculative instruction sequences with a disambiguation-free out of order load store queue |
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Instruction definition to implement load store reordering and optimization |
Gregory A. Woods |
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Virtual load store queue having a dynamic dispatch window with a unified structure |
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Method and apparatus for providing hardware support for self-modifying code |
Karthikeyan Avudaiyappan |
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Decentralized allocation of resources and interconnect structures to support the execution of instruction sequences by a plurality of engines |
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Method and system for implementing recovery from speculative forwarding miss-predictions/errors resulting from load store reordering and optimization |
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Cache replacement policy |
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2018-03-20 |
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Methods, systems and apparatus for predicting the way of a set associative cache |
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Virtual load store queue having a dynamic dispatch window with a distributed structure |
— |
2018-02-27 |
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Methods, systems and apparatus for predicting the way of a set associative cache |
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2018-02-20 |
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Method for implementing a reduced size register view data structure in a microprocessor |
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2018-02-13 |
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Method for populating and instruction view data structure by using register template snapshots |
— |
2018-02-06 |
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Systems and methods for flushing a cache with modified data |
Karthikeyan Avudaiyappan |
2018-01-02 |