Issued Patents 2018
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10078716 | Scalable logic verification by identifying unate primary inputs | Jason R. Baumgartner, Raj Kumar Gajavelly, Alexander Ivrii | 2018-09-18 |
| 10073938 | Integrated circuit design verification | Anand B. Arunagiri, Raj Kumar Gajavelly, Sujeet Kumar | 2018-09-11 |
| 9934873 | Delayed equivalence identification | Raj Kumar Gajavelly, Ashutosh Misra, Rahul M. Rao | 2018-04-03 |
| 9922153 | Scalable logic verification by identifying unate primary inputs | Jason R. Baumgartner, Raj Kumar Gajavelly, Alexander Ivrii | 2018-03-20 |