VP

Victor Markus Purri

CS Cadence Design Systems: 3 patents #4 of 223Top 2%
📍 Sunnyvale, CA: #319 of 2,644 inventorsTop 15%
🗺 California: #7,478 of 60,411 inventorsTop 15%
Overall (2018): #53,103 of 503,207Top 15%
3
Patents 2018

Issued Patents 2018

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
10108767 Methods, systems, and computer program product for implementing deadlock detection with formal verification techniques in an electronic design Michael D. Pedneau, Lars Lundgren, Pradeep Goyal 2018-10-23
9934410 Security data path verification Caio Araújo Teixeira Campos, Magnus Björk, Lawrence Loh, Claudionor Coelho 2018-04-03
9922209 Security data path verification Caio Araújo Teixeira Campos, Magnus Björk, Lawrence Loh, Claudionor Coelho 2018-03-20