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Tara Vishin

CS Cadence Design Systems: 2 patents #20 of 223Top 9%
Overall (2018): #97,306 of 503,207Top 20%
2
Patents 2018

Issued Patents 2018

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
10164524 Methods and devices for charge pump level translation in high-speed memory drivers Vinod Kumar 2018-12-25
9997214 LevelShifter-less output buffer with hybrid driver for high speed and low supply memory applications Vinod Kumar 2018-06-12