PK

Pawan Kulshreshtha

CS Cadence Design Systems: 2 patents #20 of 223Top 9%
📍 San Jose, CA: #1,359 of 5,991 inventorsTop 25%
🗺 California: #12,239 of 60,411 inventorsTop 25%
Overall (2018): #113,905 of 503,207Top 25%
2
Patents 2018

Issued Patents 2018

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
10133842 Methods, systems, and articles of manufacture for multi-mode, multi-corner physical optimization of electronic designs Amit Dhuria, Krishna Belkhale, Saulius Kersulis 2018-11-20
10037394 Hierarchical timing analysis for multi-instance blocks Amit Dhuria 2018-07-31