MO

Meir Ovadia

CS Cadence Design Systems: 2 patents #20 of 223Top 9%
Overall (2018): #120,639 of 503,207Top 25%
2
Patents 2018

Issued Patents 2018

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
10162920 System and method for performing out of order name resolution in an electronic design Jonathan Lee DeKock, Steven G. Esposito, Manu Chopra 2018-12-25
9858371 Method and system for generating post-silicon validation tests 2018-01-02