Issued Patents 2018
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10133686 | Multilevel memory bus system | Elsbeth Lauren Tagayo Villapana, Joel Alonzo Baylon | 2018-11-20 |
| 10120586 | Memory transaction with reduced latency | Rey H. Bruce, Elsbeth Lauren Tagayo-Villapaña | 2018-11-06 |
| 10013373 | Multi-level message passing descriptor | Bernard Sherwin Leung Chiw, Margaret Anne Nadonga Somera | 2018-07-03 |
| 9971524 | Scatter-gather approach for parallel data transfer in a mass storage system | Avnher Villar Santos, Marlon B. Verdan, Elsbeth Lauren Tagayo Villapana | 2018-05-15 |
| 9952991 | Systematic method on queuing of descriptors for multiple flash intelligent DMA engine operation | Marlon B. Verdan, Rowenah Michelle Jago-on | 2018-04-24 |
| 9916213 | Bus arbitration with routing and failover mechanism | Cyrill C. Ponce, Jarmie De La Cruz Espuerta, Marlon B. Verdan | 2018-03-13 |
| 9875205 | Network of memory systems | Jarmie De La Cruz Espuerta, Marlon B. Verdan | 2018-01-23 |