Issued Patents 2018
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10109479 | Method of making a semiconductor device with a buried insulating layer formed by annealing a superlattice | Robert John Stephenson, Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha | 2018-10-23 |
| 10084045 | Semiconductor device including a superlattice and replacement metal gate structure and related methods | Tsu-Jae King Liu, Hideki Takeuchi | 2018-09-25 |
| 9972685 | Vertical semiconductor devices including superlattice punch through stop layer and related methods | Hideki Takeuchi, Erwin Trautmann | 2018-05-15 |
| 9941359 | Semiconductor devices with superlattice and punch-through stop (PTS) layers at different depths and related methods | Hideki Takeuchi | 2018-04-10 |
| 9899479 | Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods | Hideki Takeuchi | 2018-02-20 |