Issued Patents 2017
Showing 26–50 of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9671462 | TAM, controller, selector, scan router, external data and control buses | — | 2017-06-06 |
| 9671464 | Bypass register separately controlled as internal scan circuit by TAP | — | 2017-06-06 |
| 9671463 | TDI, TCK, TMS, TDO, first, second, third gating routing circuit | — | 2017-06-06 |
| 9671426 | Response collector circuitry coupled with through silicon via and tap | — | 2017-06-06 |
| 9645198 | Full/reduced pin JTAG interface shadow protocol detection, command, address circuits | — | 2017-05-09 |
| 9638753 | Tap clock and enable control of scan register, flip-flop, compressor | — | 2017-05-02 |
| 9625525 | IC decompress and maskable compress TAM with SFIR and SFCR | — | 2017-04-18 |
| 9618581 | Core wrappers, I/O circuitry, link instruction register with and gate | — | 2017-04-11 |
| 9612282 | Addressable tap with address detect and control. and gating circuitry | — | 2017-04-04 |
| 9599669 | Decompressed/compressed data parallel scan paths with input/output shift register, SCI/SCO | — | 2017-03-21 |
| 9599668 | Addressable tap domain selection circuit, interface select and instruction circuitry | — | 2017-03-21 |
| 9594116 | IC die with channel circuitry, scan and BIST taps, TLM | — | 2017-03-14 |
| 9588178 | Parallel and serial data with controller, delay, and register circuits | — | 2017-03-07 |
| 9575122 | Interface with write strobe sequencer, first and second series registers | — | 2017-02-21 |
| 9575121 | Off-chip tap interface control with instruction register, multiplexer and buffer | — | 2017-02-21 |
| 9562946 | Integrated circuit wafer having plural dies with each die including test circuit receiving expected data and mask data from different pads | Alan Hales | 2017-02-07 |
| 9559025 | Scan testable through silicon VIAs | — | 2017-01-31 |
| 9551748 | Double data rate addressable tap interface with shadow protocol circuitry | — | 2017-01-24 |
| 9547042 | IR enabled gating of TAP and WSP shift, capture, transfer | — | 2017-01-17 |
| 9535122 | Serial/parallel control, separate tap, master reset synchronizer for tap domains | — | 2017-01-03 |
| 9535127 | Tester, parallel scan paths, and comparators in same functional circuits | — | 2017-01-03 |
| 9535126 | Tap, test, CSU, scan circuitry with top and bottom contacts | — | 2017-01-03 |
| 9535125 | Tap decay test circuitry having capture test strobe enable input | — | 2017-01-03 |
| 9535124 | TAP gated updateDR output AUX test control of WSP update | — | 2017-01-03 |
| 9535118 | TAP addressable circuit with bi-directional TMS and second signal lead | — | 2017-01-03 |