Issued Patents 2017
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9793923 | LDPC post-processor architecture and method for low error floor conditions | Yaoyu Tao | 2017-10-17 |
| 9711715 | Method of manufacturing a dual mode ferroelectric random access memory (FRAM) having imprinted read-only (RO) data | Chiraag Juvekar, Clive Bittlestone, Srinath Ramaswamy, Stephen Keith Heinrich-Barna | 2017-07-18 |