Issued Patents 2017
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9754999 | Vertical thin film transistors with surround gates | Manabu Hayashi, Ryousuke Itou, Takuro Maede, Kengo Kajiwara, Tetsuya Yamada +1 more | 2017-09-05 |
| 9748172 | Floating staircase word lines and process in a 3D non-volatile memory having vertical bit lines | — | 2017-08-29 |
| 9698202 | Parallel bit line three-dimensional resistive random access memory | — | 2017-07-04 |
| 9673257 | Vertical thin film transistors with surround gates | Manabu Hayashi, Akira Nakada, Ryousuke Itou, Takuro Maede, Kengo Kajiwara +1 more | 2017-06-06 |
| 9646880 | Monolithic three dimensional memory arrays formed using sacrificial polysilicon pillars | Teruyuki Mine | 2017-05-09 |
| 9613689 | Self-selecting local bit line for a three-dimensional memory array | — | 2017-04-04 |
| 9595566 | Floating staircase word lines and process in a 3D non-volatile memory having vertical bit lines | — | 2017-03-14 |
| 9583539 | Word line connection for memory device and method of making thereof | — | 2017-02-28 |