Issued Patents 2017
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9846650 | Tail response time reduction method for SSD | Mu-Tien Chang, Dimin Niu | 2017-12-19 |
| 9837135 | Methods for addressing high capacity SDRAM-like memory without increasing pin cost | Mu-Tien Chang, Dimin Niu, Sun-Young Lim, Indong Kim, Jangseok Choi | 2017-12-05 |
| 9830086 | Hybrid memory controller for arbitrating access to volatile and non-volatile memories in a hybrid memory group | Dimin Niu, Mu-Tien Chang, Sun-Young Lim, Indong Kim | 2017-11-28 |
| 9785570 | Memory devices and modules | Chaohong Hu, Dimin Niu | 2017-10-10 |
| 9772900 | Tiered ECC single-chip and double-chip Chipkill scheme | Chaohong Hu, Uksong Kang | 2017-09-26 |
| 9761296 | Smart in-module refresh for DRAM | Mu-Tien Chang, Krishna T. Malladi, Dimin Niu | 2017-09-12 |
| 9754684 | Completely utilizing hamming distance for SECDED based ECC DIMMs | Chaohong Hu, Prashant Jayaprakash Nair | 2017-09-05 |
| 9727239 | Electronic system with partitioning mechanism and method of operation thereof | Dimin Niu, Krishna Suhas, Krishna T. Malladi | 2017-08-08 |
| 9710226 | Unsuccessful write retry buffer | Brent Haukness | 2017-07-18 |
| 9696923 | Reliability-aware memory partitioning mechanisms for future memory technologies | Dimin Niu, Mu-Tien Chang | 2017-07-04 |
| 9577644 | Reconfigurable logic architecture | Mingyu Gao, Krishna T. Malladi, Robert Brennan | 2017-02-21 |
| 9569359 | Methods and apparatuses for addressing memory caches | Trung Diep | 2017-02-14 |
| 9569393 | Memory module threading with staggered data transfers | Frederick A. Ware | 2017-02-14 |