Issued Patents 2017
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9786663 | Layout construction for addressing electromigration | Seid Hadi Rasouli, Ohsang Kwon | 2017-10-10 |
| 9678154 | Circuit techniques for efficient scan hold path design | Qi Ye, Steven James Dillen | 2017-06-13 |
| 9673786 | Flip-flop with reduced retention voltage | Seid Hadi Rasouli, Jay M. Shah, Martin Saint-Laurent, Peeyush Kumar Parkar, Sachin Bapat +3 more | 2017-06-06 |
| 9584121 | Compact design of scan latch | Qi Ye, Zhengyu Duan, Steven James Dillen | 2017-02-28 |
| 9577635 | Clock-gating cell with low area, low power, and low setup time | Seid Hadi Rasouli, Steven James Dillen | 2017-02-21 |
| 9564881 | Area-efficient metal-programmable pulse latch design | Qi Ye, Steven James Dillen, Zhengyu Duan, Satyanarayana Sahu, Praveen Narendranath | 2017-02-07 |