Issued Patents 2017
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9766972 | Masking defective bits in a storage array | John D. Davis, John Hayes, Zhangxi Tan, Nenad Miladinovic | 2017-09-19 |
| 9747158 | Intelligent refresh of 3D NAND | Robert Lee, Yuhong Mao | 2017-08-29 |
| 9652371 | Lookahead scheme for prioritized reads | Rajat Goel, Khurram Z. Malik | 2017-05-16 |
| 9563575 | Least recently used mechanism for cache line eviction from a cache memory | Brian P. Lilly, Gerard R. Williams, III, Mahnaz Sadoughi-Yarandi, Perumal R. Subramonium, Prashant Jain | 2017-02-07 |
| 9563567 | Selective cache way-group power down | Mahnaz Sadoughi-Yarandi, Perumal R. Subramonium, Brian P. Lilly | 2017-02-07 |
| 9558069 | Failure mapping in a storage array | John D. Davis, John Hayes, Zhangxi Tan, Nenad Miladinovic | 2017-01-31 |
| 9535695 | Completing load and store instructions in a weakly-ordered memory model | John H. Mylius, Rajat Goel, Pradeep Kanapathipillai | 2017-01-03 |