Issued Patents 2017
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9792117 | Loading values from a value vector into subregisters of a single instruction multiple data register | Amit Ganesh, Shasank K. Chavan, Vineet Marwah, Jesse Kamp, Michael J. Gleeson +2 more | 2017-10-17 |
| 9697174 | Efficient hardware instructions for processing bit vectors for single instruction multiple data processors | Amit Ganesh, Shasank K. Chavan, Vineet Marwah, Jesse Kamp, Michael J. Gleeson +2 more | 2017-07-04 |
| 9697221 | OZIP compression and decompression | Victor Chen, Shasank K. Chavan, Jesse Kamp, Amit Ganesh, Vineet Marwah | 2017-07-04 |