| 9823931 |
Queued instruction re-dispatch after runahead |
Guillermo J. Rozas, Alexander Klaiber, James van Zoeren, Paul Serris, Brad Hoyt +6 more |
2017-11-21 |
| 9740553 |
Managing potentially invalid results during runahead |
Bruce Holmer, Guillermo J. Rozas, Alexander Klaiber, James van Zoeren, Paul Serris +5 more |
2017-08-22 |
| 9632976 |
Lazy runahead operation for a microprocessor |
Guillermo J. Rozas, Alexander Klaiber, James van Zoeren, Paul Serris, Brad Hoyt +4 more |
2017-04-25 |
| 9563432 |
Dynamic configuration of processing pipeline based on determined type of fetched instruction |
Darrell D. Boggs, Shiaoli Mendyke |
2017-02-07 |
| 9552032 |
Branch prediction power reduction |
Aneesh Aggarwal, Kevin Koschoreck, Paul Wasson |
2017-01-24 |
| 9547358 |
Branch prediction power reduction |
Aneesh Aggarwal, Paul Wasson |
2017-01-17 |