Issued Patents 2017
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9710359 | Executing debug program instructions on a target apparatus processing pipeline | Chiloda Ashan Senerath Pathirane | 2017-07-18 |
| 9665494 | Parallel lookup in first and second value stores | Chiloda Ashan Senerath Pathirane | 2017-05-30 |
| 9658919 | Malfunction escalation | Chiloda Ashan Senerath Pathirane | 2017-05-23 |
| 9645824 | Branch target address cache using hashed fetch addresses | Vladimir Vasekin, Chiloda Ashan Senerath Pathirane, Jean-Baptiste Brelot | 2017-05-09 |