Issued Patents 2017
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9767904 | Memory with three transistor memory cell device | Peter Feeley | 2017-09-19 |
| 9734915 | Shielded vertically stacked data line architecture for memory | — | 2017-08-15 |
| 9679650 | 3D NAND memory Z-decoder | — | 2017-06-13 |
| 9583154 | Methods and apparatuses including a string of memory cells having a first select transistor coupled to a second select transistor | — | 2017-02-28 |
| 9553103 | Memory cell profiles | — | 2017-01-24 |
| 9536618 | Apparatuses and methods to control body potential in memory operations | Han Zhao, Akira Goda, Krishna K. Parat, Aurielo Giancarlo Mauri, Haitao Liu +2 more | 2017-01-03 |