Issued Patents 2017
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9837149 | Low read current architecture for memory | Bruce L. Bateman, Darrell Rinerson, Chang Hua Siau | 2017-12-05 |
| 9831425 | Two-terminal reversibly switchable memory device | Darrell Rinerson, Wayne Kinney, Roy Lambertson, John Sanchez, Lawrence Schloss +2 more | 2017-11-28 |
| 9830985 | Preservation circuit and methods to maintain values representing data in one or more layers of memory | Robert Norman | 2017-11-28 |
| 9830974 | SRAM with active substrate bias | Scott Hanson | 2017-11-28 |
| 9806130 | Memory element with a reactive metal layer | Steve Kuo-Ren Hsia, Wayne Kinney, Steven W. Longcor, Darrell Rinerson, John Sanchez +2 more | 2017-10-31 |
| 9779788 | Sub-threshold enabled flash memory system | Daniel Martin Cermak, Scott Hanson | 2017-10-03 |
| 9767899 | Access signal conditioning for memory cells in an array | Chang Hua Siau | 2017-09-19 |
| 9748223 | Six-transistor SRAM semiconductor structures and methods of fabrication | Harry Luan, Bruce L. Bateman, Valery Axelrad, Charlie Cheng | 2017-08-29 |
| 9711212 | High voltage switching circuitry for a cross-point array | Chang Hua Siau | 2017-07-18 |
| 9613968 | Cross-coupled thyristor SRAM semiconductor structures and methods of fabrication | Harry Luan, Bruce L. Bateman, Valery Axelrad, Charlie Cheng | 2017-04-04 |
| 9570515 | Memory element with a reactive metal layer | Steve Kuo-Ren Hsia, Wayne Kinney, Steven W. Longcor, Darrell Rinerson, John Sanchez +2 more | 2017-02-14 |
| 9570165 | 1D-2R memory architecture | Deepak C. Sekar, Gary B. Bronner, Lidia Vereen, Philip Swab, Elizabeth Friend +1 more | 2017-02-14 |
| 9564198 | Six-transistor SRAM semiconductor structures and methods of fabrication | Harry Luan, Bruce L. Bateman, Valery Axelrad, Charlie Cheng | 2017-02-07 |
| 9564441 | Two-transistor SRAM semiconductor structure and methods of fabrication | Harry Luan, Bruce L. Bateman, Valery Axelrad, Charlie Cheng | 2017-02-07 |
| 9536607 | Preservation circuit and methods to maintain values representing data in one or more layers of memory | Robert Norman | 2017-01-03 |