Issued Patents 2017
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9798352 | Circuits for and methods of implementing a design for testing and debugging with dual-edge clocking | Balakrishna Jayadev | 2017-10-24 |
| 9761533 | Interposer-less stack die interconnect | Raghunandan Chaware, Glenn O'Rourke, Inderjit Singh | 2017-09-12 |
| 9600018 | Clock stoppage in integrated circuits with multiple asynchronous clock domains | Balakrishna Jayadev, Ismed D. Hartanto | 2017-03-21 |