Issued Patents 2017
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9846571 | Utilizing clock rate pipelining to generate code for multi-rate systems | Girish Venkataramani, Wang Chen | 2017-12-19 |
| 9817931 | Systems and methods for generating optimized hardware descriptions for models | Girish Venkataramani, Rama Kokku | 2017-11-14 |
| 9779195 | Model-based retiming with functional equivalence constraints | Girish Venkataramani | 2017-10-03 |