Issued Patents 2017
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9842652 | Memory array with power-efficient read architecture | — | 2017-12-12 |
| 9786334 | Interconnections for 3D memory | — | 2017-10-10 |
| 9778846 | Sequential memory access operations | — | 2017-10-03 |
| 9780110 | Memory having memory cell string and coupling components | — | 2017-10-03 |
| 9779819 | Connecting memory cells to a data line sequentially while applying a program voltage to the memory cells | Qiang Tang, Ramin Ghodsi | 2017-10-03 |
| 9779791 | Apparatuses and methods involving accessing distributed sub-blocks of memory cells | — | 2017-10-03 |
| 9773553 | Segmented memory and operation | Han Zhao | 2017-09-26 |
| 9773564 | Memory read apparatus and methods | — | 2017-09-26 |
| 9747991 | Random telegraph signal noise reduction scheme for semiconductor memories | — | 2017-08-29 |
| 9728538 | Three-dimensional devices having reduced contact length | — | 2017-08-08 |
| 9727417 | Chunk redundancy architecture for memory | — | 2017-08-08 |
| 9721960 | Data line arrangement and pillar arrangement in apparatuses | — | 2017-08-01 |
| 9711514 | Methods and apparatuses including a select transistor having a body region including monocrystalline semiconductor material and/or at least a portion of its gate located in a substrate | — | 2017-07-18 |
| 9711228 | Apparatus and methods of operating memory with erase de-bias | — | 2017-07-18 |
| 9711224 | Devices including memory arrays, row decoder circuitries and column decoder circuitries | — | 2017-07-18 |
| 9704876 | Semiconductor apparatus with multiple tiers, and methods | — | 2017-07-11 |
| 9697907 | Apparatuses and methods using dummy cells programmed to different states | Aaron Yip | 2017-07-04 |
| 9646660 | Selectable memory access time | — | 2017-05-09 |
| 9641068 | Voltage generator circuit | — | 2017-05-02 |
| 9614516 | Devices for shielding a signal line over an active region | — | 2017-04-04 |
| 9607705 | Apparatuses and methods for charging a global access line prior to accessing a memory | — | 2017-03-28 |
| 9595533 | Memory array having connections going through control gates | Tamotsu Murakoshi, Deepak Thimmegowda | 2017-03-14 |
| 9536618 | Apparatuses and methods to control body potential in memory operations | Han Zhao, Akira Goda, Krishna K. Parat, Aurielo Giancarlo Mauri, Haitao Liu +2 more | 2017-01-03 |
| 9536582 | Enable/disable of memory chunks during memory access | Satoru Tamada, Koichi Kawai, Tetsuji Manabe | 2017-01-03 |