Issued Patents 2017
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9825186 | Read performance of a non-volatile memory device, in particular a non-volatile memory device with buried selection transistor | Francesco La Rosa, Arnaud Regnier | 2017-11-21 |
| 9691866 | Memory cell having a vertical selection gate formed in an FDSOI substrate | Arnaud Regnier, Jean-Michel Mirabel, Francesco La Rosa | 2017-06-27 |
| 9666484 | Integrated circuit protected from short circuits caused by silicide | Arnaud Regnier, Francesco La Rosa | 2017-05-30 |
| 9653470 | Individually read-accessible twin memory cells | Francesco La Rosa, Arnaud Regnier | 2017-05-16 |
| 9627068 | Twin memory cell interconnection structure | Francesco La Rosa, Arnaud Regnier | 2017-04-18 |
| 9613709 | Dual non-volatile memory cell comprising an erase transistor | Francesco La Rosa, Arnaud Regnier | 2017-04-04 |
| 9543311 | Vertical memory cell with non-self-aligned floating drain-source implant | Marc Mantelli, Arnaud Regnier, Francesco La Rosa, Julien Delalleau | 2017-01-10 |