Issued Patents 2017
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9842005 | Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines | — | 2017-12-12 |
| 9842056 | Systems and methods for non-blocking implementation of cache flush instructions | Karthikeyan Avudaiyappan | 2017-12-12 |
| 9817666 | Method for a delayed branch implementation by using a front end track table | — | 2017-11-14 |
| 9811342 | Method for performing dual dispatch of blocks and half blocks | — | 2017-11-07 |
| 9766893 | Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines | — | 2017-09-19 |
| 9753856 | Variable caching structure for managing physical storage | — | 2017-09-05 |
| 9753691 | Method for a stage optimized high speed adder | — | 2017-09-05 |
| 9753734 | Method and apparatus for sorting elements in hardware structures | Mandeep Singh | 2017-09-05 |
| 9740612 | Systems and methods for maintaining the coherency of a store coalescing cache and a load cache | Karthikeyan Avudaiyappan | 2017-08-22 |
| 9697131 | Variable caching structure for managing physical storage | — | 2017-07-04 |
| 9678755 | Instruction sequence buffer to enhance branch prediction efficiency | — | 2017-06-13 |
| 9678882 | Systems and methods for non-blocking implementation of cache flush instructions | Karthikeyan Avudaiyappan | 2017-06-13 |