Issued Patents 2017
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9825186 | Read performance of a non-volatile memory device, in particular a non-volatile memory device with buried selection transistor | Stephan Niel, Arnaud Regnier | 2017-11-21 |
| 9792962 | Sense amplifier for memory device | Gineuve Alieri | 2017-10-17 |
| 9714976 | Circuit and method for detecting a fault attack | — | 2017-07-25 |
| 9698765 | Dynamic sense amplifier with offset compensation | Antonino Conte | 2017-07-04 |
| 9691866 | Memory cell having a vertical selection gate formed in an FDSOI substrate | Arnaud Regnier, Jean-Michel Mirabel, Stephan Niel | 2017-06-27 |
| 9666484 | Integrated circuit protected from short circuits caused by silicide | Arnaud Regnier, Stephan Niel | 2017-05-30 |
| 9653470 | Individually read-accessible twin memory cells | Stephan Niel, Arnaud Regnier | 2017-05-16 |
| 9627068 | Twin memory cell interconnection structure | Stephan Niel, Arnaud Regnier | 2017-04-18 |
| 9627011 | Sense amplifier circuit with offset compensation for a non-volatile memory device | Antonino Conte | 2017-04-18 |
| 9613709 | Dual non-volatile memory cell comprising an erase transistor | Stephan Niel, Arnaud Regnier | 2017-04-04 |
| 9570513 | Vertical bipolar transistor | Philippe Boivin, Julien Delalleau | 2017-02-14 |
| 9543018 | Non-volatile memory with a variable polarity line decoder | — | 2017-01-10 |
| 9543311 | Vertical memory cell with non-self-aligned floating drain-source implant | Marc Mantelli, Stephan Niel, Arnaud Regnier, Julien Delalleau | 2017-01-10 |