Issued Patents 2017
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9645819 | Method and apparatus for reducing area and complexity of instruction wakeup logic in a multi-strand out-of-order processor | Jayesh Iyer, Nikolay Kosarev, Sergey Y. Shishlov, Alexander V. Butuzov, Boris A. Babayan +1 more | 2017-05-09 |
| 9632790 | Select logic for the instruction scheduler of a multi strand out-of-order processor based on delayed reconstructed program order | Jayesh Iyer, Nikolay Kosarev, Sergey Y. Shishlov, Yuriy V Baida, Alexander V. Butuzov +2 more | 2017-04-25 |