Issued Patents 2017
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9853046 | Apparatuses and methods for forming multiple decks of memory cells | Zhenyu Lu, Roger W. Lindsay, John D. Hopkins | 2017-12-26 |
| 9793282 | Floating gate memory cells in vertical memory | Charles H. Dennison, John D. Hopkins, Fatma Arzum Simsek-Ege, Krishna K. Parat | 2017-10-17 |
| 9786375 | Multiple blocks per string in 3D NAND memory | Graham R. Wolstenholme, Tomoharu Tanaka | 2017-10-10 |
| 9779829 | Erasing memory segments in a memory block of memory cells using select gate control line voltages | Christian Caillat | 2017-10-03 |
| 9779817 | Boosting channels of memory cells to reduce program disturb | Violante Moschiano, Mason Jones | 2017-10-03 |
| 9779816 | Apparatus and methods including source gates | Shafqat Ahmed, Khaled Hasnat, Krishna K. Parat | 2017-10-03 |
| 9754671 | Programming methods and memories | Yijie Zhao | 2017-09-05 |
| 9741737 | Integrated structures comprising vertical channel material and having conductively-doped semiconductor material directly against lower sidewalls of the channel material | Guangyu Huang, Haitao Liu, Chandra Mouli, Justin B. Dorhout, Sanh D. Tang | 2017-08-22 |
| 9728266 | Memory device including multiple select gates and different bias conditions | Haitao Liu, Changhyun Lee | 2017-08-08 |
| 9679778 | Methods of forming memory cells with air gaps and other low dielectric constant materials | Minsoo Lee | 2017-06-13 |
| 9672102 | NAND memory devices systems, and methods using pre-read error recovery protocols of upper and lower pages | Pranav Kalavade, Charan Srinivasan | 2017-06-06 |
| 9646702 | Operating memory devices to apply a programming potential to a memory cell in a string coupled to a source and data line concurrently with biasing the data line to a greater potential than the source | Yijie Zhao, Krishna K. Parat | 2017-05-09 |
| 9633719 | Programming memory cells to be programmed to different levels to an intermediate level from a lowest level | Carmine Miccoli, Christian Caillat | 2017-04-25 |
| 9576667 | Apparatuses and methods for non-volatile memory programming schemes | William C. Filipiak | 2017-02-21 |
| 9564227 | Memory device having a different source line coupled to each of a plurality of layers of memory cell arrays | Zengtao T. Liu | 2017-02-07 |
| 9536618 | Apparatuses and methods to control body potential in memory operations | Han Zhao, Krishna K. Parat, Aurielo Giancarlo Mauri, Haitao Liu, Toru Tanzawa +2 more | 2017-01-03 |