Issued Patents 2017
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9818492 | Method for testing a memory and memory system | — | 2017-11-14 |
| 9645883 | Circuit arrangement and method for realizing check bit compacting for cross parity codes | Sven Hosp, Michael Goessel | 2017-05-09 |
| 9646716 | Circuit arrangement and method with modified error syndrome for error detection of permanent errors in memories | Michael Goessel, Sven Hosp, Guenther Niess | 2017-05-09 |