Issued Patents 2017
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9747400 | Optimizing placement of circuit resources using a globally accessible placement memory | David J. Hathaway, Nathaniel D. Hieter, Alexander J. Suess | 2017-08-29 |
| 9715572 | Hierarchical wire-pin co-optimization | Christopher J. Berry, Ajith Kumar M. Chandrasekaran, Randall J. Darden, Sourav Saha | 2017-07-25 |
| 9703914 | Optimizing placement of circuit resources using a globally accessible placement memory | David J. Hathaway, Nathaniel D. Hieter, Alexander J. Suess | 2017-07-11 |
| 9697322 | Hierarchical wire-pin co-optimization | Christopher J. Berry, Ajith Kumar M. Chandrasekaran, Randall J. Darden, Sourav Saha | 2017-07-04 |