Issued Patents 2017
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9773570 | Built-in-self-test (BIST) test time reduction | Kevin W. Gorman, Deepak I. Hanagandi, Krishnendu Mondal | 2017-09-26 |
| 9761329 | Built-in self-test (BIST) circuit and associated BIST method for embedded memories | Aravindan J. Busi, Deepak I. Hanagandi, Krishnendu Mondal | 2017-09-12 |
| 9734920 | Memory test with in-line error correction code logic to test memory data and test the error correction code logic surrounding the memories | Kevin W. Gorman, Patrick E. Perry | 2017-08-15 |
| 9715942 | Built-in self-test (BIST) circuit and associated BIST method for embedded memories | Aravindan J. Busi, Deepak I. Hanagandi, Krishnendu Mondal | 2017-07-25 |
| 9672185 | Method and system for enumerating digital circuits in a system-on-a-chip (SOC) | Thomas Chadwick, Nancy H. Pratt | 2017-06-06 |