Issued Patents 2017
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9740807 | Method to measure edge-rate timing penalty of digital integrated circuits | Nitin Mohan | 2017-08-22 |
| 9601181 | Controlled multi-step de-alignment of clocks | David Lin, Edward Wade Thoenes | 2017-03-21 |