YK

Yael Kinderman

CS Cadence Design Systems: 3 patents #8 of 238Top 4%
Overall (2017): #54,080 of 506,227Top 15%
3
Patents 2017

Issued Patents 2017

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
9824175 Method and system of evaluation of validity of a refinement rule for a hardware emulation Hemant Gupta, Nili Segal, Oded Oren 2017-11-21
9582458 Generation of a random sub-space of the space of assignments for a set of generative attributes for verification coverage closure Efrat Gavish, Meirav O. Nitzan 2017-02-28
9582620 Method and system for automated refined exclusion of entities from a metric driven verification analysis score Nili Segal, Hemant Gupta, Oded Oren 2017-02-28