VB

Vuk Borich

CS Cadence Design Systems: 2 patents #21 of 238Top 9%
📍 San Jose, CA: #1,429 of 5,952 inventorsTop 25%
🗺 California: #13,043 of 60,394 inventorsTop 25%
Overall (2017): #95,179 of 506,227Top 20%
2
Patents 2017

Issued Patents 2017

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
9779188 Harmonic balance analysis memory usage estimation Yue Li 2017-10-03
9589085 Systems and methods for viewing analog simulation check violations in an electronic design automation framework Donald J. O'Riordan, Keith Dennison 2017-03-07