VS

Viktor Salitrennik

CS Cadence Design Systems: 1 patents #55 of 238Top 25%
📍 Berkeley, CA: #192 of 534 inventorsTop 40%
🗺 California: #24,257 of 60,394 inventorsTop 45%
Overall (2017): #203,910 of 506,227Top 45%
1
Patents 2017

Issued Patents 2017

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
9646120 Method and system for trace compaction during emulation of a circuit design Beshara Elmufdi, Mitchell G. Poplack 2017-05-09