SS

Steven Shrader

CS Cadence Design Systems: 1 patents #55 of 238Top 25%
📍 Meridian, ID: #27 of 80 inventorsTop 35%
🗺 Idaho: #325 of 925 inventorsTop 40%
Overall (2017): #232,389 of 506,227Top 50%
1
Patents 2017

Issued Patents 2017

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
9703625 Method and apparatus for detecting or correcting multi-bit errors in computer memory systems Marc A. Greenberg 2017-07-11