NK

Navneet Kaushik

CS Cadence Design Systems: 1 patents #55 of 238Top 25%
Overall (2017): #297,766 of 506,227Top 60%
1
Patents 2017

Issued Patents 2017

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
9640280 Power domain aware insertion methods and designs for testing and repairing memory Puneet Arora, Steven Lee Gregor, Norman Robert Card 2017-05-02