AK

An-Yu Kuo

CS Cadence Design Systems: 2 patents #21 of 238Top 9%
📍 San Jose, CA: #1,429 of 5,952 inventorsTop 25%
🗺 California: #13,043 of 60,394 inventorsTop 25%
Overall (2017): #170,981 of 506,227Top 35%
2
Patents 2017

Issued Patents 2017

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
9785141 Method, system, and computer program product for schematic driven, unified thermal and electromagnetic interference compliance analyses for electronic circuit designs Alok Tripathi, Bradley Brim, Taranjit Singh Kukal 2017-10-10
9672319 Methods, systems, and articles of manufacture for implementing electronic designs with a pseudo-3D analysis mechanism Xiande Cao, Jian Liu 2017-06-06