Issued Patents 2017
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9721057 | System and method for netlist clock domain crossing verification | Malay Ganai, Maher Mneimneh, Paras Mal Jain, Mohammad H. Movahed-Ezazi, Pronay Kumar Biswas +1 more | 2017-08-01 |
| 9721058 | System and method for reactive initialization based formal verification of electronic logic design | Hans-Jorg Peter, Barsneya Chakrabarti, Fahim Rahim, Mohammad H. Movahed-Ezazi | 2017-08-01 |