Issued Patents 2017
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9838025 | Method for reducing lock time in a closed loop clock signal generator | Wei Deng, Gin Yee | 2017-12-05 |
| 9692426 | Phase locked loop system with bandwidth measurement and calibration | Meei-Ling Chiang, Boon-Aik Ang | 2017-06-27 |