Issued Patents 2016
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9330215 | Method and system for verifying the design of an integrated circuit having multiple tiers | Chi-Ting Huang, Cheng-Hung Yeh, Hsien-Hsin Sean Lee | 2016-05-03 |
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9330215 | Method and system for verifying the design of an integrated circuit having multiple tiers | Chi-Ting Huang, Cheng-Hung Yeh, Hsien-Hsin Sean Lee | 2016-05-03 |