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Method of forming split-gate memory cell array along with low and high voltage logic devices |
Man-Tang Wu, Jeng-Wei Yang, Chien-Sheng Su, Chun-Ming Chen |
2016-11-15 |
| 9431407 |
Method of making embedded memory device with silicon-on-insulator substrate |
Chien-Sheng Su, Hieu Van Tran, Mandana Tadayoni, Jeng-Wei Yang |
2016-08-30 |
| 9330922 |
Self-aligned stack gate structure for use in a non-volatile memory array and a method of forming such structure |
Willem-Jan Toren, Xian Liu, Gerhard Metzger-Brueckl, Stephan Wege, Nadia Miridi +7 more |
2016-05-03 |
| 9306039 |
Method of making split-gate memory cell with substrate stressor region |
Mandana Tadayoni |
2016-04-05 |
| 9293359 |
Non-volatile memory cells with enhanced channel region effective width, and method of making same |
Hieu Van Tran, Chien-Sheng Su, Prateep Tuntasood |
2016-03-22 |
| 9293204 |
Non-volatile memory cell with self aligned floating and erase gates, and method of making same |
Jinho Kim, Xian Liu |
2016-03-22 |
| 9286982 |
Flash memory system with EEPROM functionality |
Hieu Van Tran, Hung Quoc Nguyen, Vipin Tiwari |
2016-03-15 |
| 9276005 |
Non-volatile memory array with concurrently formed low and high voltage logic devices |
Feng Zhou, Xian Liu |
2016-03-01 |
| 9275748 |
Low leakage, low threshold voltage, split-gate flash cell operation |
Steven Lemke, Jinho Kim, Jong-Won Yoo, Alexander Kotov, Yuri Tkachev |
2016-03-01 |
| 9245638 |
Method of operating a split gate flash memory cell with coupling gate |
Elizabeth Cuevas, Yuri Tkachev, Mandana Tadayoni, Henry A. Om'Mani |
2016-01-26 |