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Apparatus and method for processing invalid operation in prologue or epilogue of loop |
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Apparatus and method for executing external operations in prologue or epilogue of a software-pipelined loop |
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| 9354850 |
Method and apparatus for instruction scheduling using software pipelining |
Min-Wook Ahn, Tai-Song Jin, Seung Won Lee, Jin Seok Lee |
2016-05-31 |
| 9311270 |
Scheduler and scheduling method for reconfigurable architecture |
Yoonseo Choi, Hae-Woo Park |
2016-04-12 |
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Reconfigurable processor using power gating, compiler and compiling method thereof |
Sung-Joo Ben Yoo, Yeon-Gon Cho, Bernhard Egger, Hee-Jin Ahn |
2016-04-05 |
| 9286074 |
NOP instruction compressing apparatus and method in a VLIW machine |
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2016-03-15 |
| 9262162 |
Register file and computing device using the same |
Bernhard Egger, Dong-Hoon Yoo |
2016-02-16 |
