Issued Patents 2016
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9519603 | Method and apparatus to enable multiple masters to operate in a single master bus architecture | Richard Dominic Wietfeldt, George Alan Wiley | 2016-12-13 |
| 9490964 | Symbol transition clocking clock and data recovery to suppress excess clock caused by symbol glitch during stable symbol period | — | 2016-11-08 |
| 9444612 | Multi-wire single-ended push-pull link with data symbol transition based clocking | George Alan Wiley, Joseph Cheung | 2016-09-13 |
| 9426082 | Low-voltage differential signaling or 2-wire differential link with symbol transition clocking | — | 2016-08-23 |
| 9374216 | Multi-wire open-drain link with data symbol transition based clocking | Joseph Cheung, George Alan Wiley | 2016-06-21 |
| 9363071 | Circuit to recover a clock signal from multiple wire data signals that changes state every state cycle and is immune to data inter-lane skew as well as data state transition glitches | Chulkyu Lee, George Alan Wiley, Joseph Cheung | 2016-06-07 |
| 9337997 | Transcoding method for multi-wire signaling that embeds clock information in transition of signal state | George Alan Wiley, Chulkyu Lee, Joseph Cheung | 2016-05-10 |
| 9319178 | Method for using error correction codes with N factorial or CCI extension | — | 2016-04-19 |
| 9313058 | Compact and fast N-factorial single data rate clock and data recovery circuits | George Alan Wiley, Chulkyu Lee | 2016-04-12 |