| 9477480 |
System and processor for implementing interruptible batches of instructions |
Olivier Giroux, Robert Ohannessian, Michael A. Fetterman |
2016-10-25 |
| 9477482 |
System, method, and computer program product for implementing multi-cycle register file bypass |
Xiaogang Qiu, Ian Kwong, Ming Y. Siu, Michael A. Fetterman |
2016-10-25 |
| 9471307 |
System and processor that include an implementation of decoupled pipelines |
Olivier Giroux, Michael A. Fetterman, Robert Ohannessian, Shirish Gadre, Xiaogang Qiu +2 more |
2016-10-18 |
| 9430242 |
Throttling instruction issue rate based on updated moving average to avoid surges in DI/DT |
Peter Nelson, Olivier Giroux |
2016-08-30 |
| 9361114 |
Instruction based interrupt masking for managing interrupts in a computer environment |
Gil Tene, Scott D. Sellers, Michael A. Wolf |
2016-06-07 |
| 9336005 |
Cooperative preemption |
Gil Tene, Michael A. Wolf, Scott D. Sellers |
2016-05-10 |