Issued Patents 2016
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9514834 | Retention logic for non-volatile memory | Nai-Ping Kuo, Kuen-Long Chang, Ken-Hui Chen, Yu-Chen Wang | 2016-12-06 |
| 9508455 | Memory device and operating method thereof for reducing interference between memory cells | Chung-Kuang Chen, Han-Sung Chen | 2016-11-29 |
| 9502121 | Method and apparatus for reducing erase time of memory by using partial pre-programming | Chun-Yi Lee, Kuen-Long Chang | 2016-11-22 |
| 9496015 | Array structure having local decoders in an electronic device | Ming-Hsiu Lee, Tien-Yen Wang | 2016-11-15 |
| 9490624 | Circuit for voltage detection and protection and operating method thereof | Yu-Meng Chaung, Kuen-Long Chang, Ken-Hui Chen | 2016-11-08 |
| 9471485 | Difference L2P method | Lung-Yi Kuo, Hsin-Yi Ho, Han-Sung Chen | 2016-10-18 |
| 9449666 | Local word line driver | Chung-Kuang Chen, Han-Sung Chen | 2016-09-20 |
| 9450577 | Circuit with output switch | Kuen-Long Chang, Ken-Hui Chen, Su-Chueh Lo, Tzu-Ting Chiu | 2016-09-20 |
| 9444462 | Stabilization of output timing delay | Yu-Meng Chaung, Kuen-Long Chang, Ken-Hui Chen | 2016-09-13 |
| 9437264 | Memory operation latency control | Han-Sung Chen, Ming-Chao Lin | 2016-09-06 |
| 9423814 | Apparatus of supplying power while maintaining its output power signal and method therefor | Chih-Ting Hu, Wu-Chin Peng, Kuen-Long Chang, Ken-Hui Chen | 2016-08-23 |
| 9412460 | Plural operation of memory device | Tzung-Shen Chen, Shuo Nan Hong, Yi-Ching Liu | 2016-08-09 |
| 9396770 | Method and apparatus for adjusting drain bias of a memory cell with addressed and neighbor bits | Han-Sung Chen, Chung-Kuang Chen | 2016-07-19 |
| 9368220 | Non-volatile memory device and method for shortened erase operation during testing | Kuen-Long Chang, Ken-Hui Chen, Nai-Ping Kuo, Chin-Hung Chang, Chang-Ting Chen | 2016-06-14 |
| 9349469 | Program verify with multiple sensing | Chung-Kuang Chen, Han-Sung Chen | 2016-05-24 |
| 9286158 | Programming method, reading method and operating system for memory | Chien-Hsin Liu, Su-Chueh Lo, Kuen-Long Chang, Ken-Hui Chen | 2016-03-15 |
| 9281021 | Method and apparatus for reduced read latency for consecutive read operations of memory of an integrated circuit | Han-Sung Chen, Ming-Chao Lin | 2016-03-08 |
| 9270272 | Clock integrated circuit | Chung-Kuang Chen, Han-Sung Chen | 2016-02-23 |
| 9245644 | Method and apparatus for reducing erase disturb of memory by using recovery bias | Bo-Chang Wu, Kuen-Long Chang, Ken-Hui Chen | 2016-01-26 |