Issued Patents 2016
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9425110 | Yield enhancing vertical redundancy method for 3D wafer level packaged (WLP) integrated circuit systems | Jose G. Padilla, Philip W. Hon, Shih-En Shih, Roger Tsai | 2016-08-23 |