Issued Patents 2016
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9520862 | Dual-port negative level sensitive reset preset data retention latch | Sudhanshu Khanna | 2016-12-13 |
| 9520863 | Dual-port negative level sensitive preset data retention latch | Sudhanshu Khanna | 2016-12-13 |
| 9454437 | Non-volatile logic based processing device | Andreas Waechter, Mark Jung, Sudhanshu Khanna | 2016-09-27 |
| 9342259 | Nonvolatile logic array and power domain segmentation in processing device | Sudhanshu Khanna | 2016-05-17 |
| 9335954 | Customizable backup and restore from nonvolatile logic array | Sudhanshu Khanna | 2016-05-10 |
| 9270257 | Dual-port positive level sensitive reset data retention latch | Sudhanshu Khanna | 2016-02-23 |