Issued Patents 2016
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9530734 | Enforcement of semiconductor structure regularity for localized transistors and interconnect | Stephen Kornachuk, Jim Mali, Carole Lambert | 2016-12-27 |
| 9530795 | Methods for cell boundary encroachment and semiconductor devices implementing the same | Jonathan R. Quandt, Dhrumil Gandhi | 2016-12-27 |
| 9443947 | Semiconductor chip including region having integrated circuit transistor gate electrodes formed by various conductive structures of specified shape and position and method for manufacturing the same | Michael C. Smayling | 2016-09-13 |
| 9424387 | Methods for cell phasing and placement in dynamic array architecture and implementation of the same | Jonathan R. Quandt, Dhrumil Gandhi | 2016-08-23 |
| 9425273 | Semiconductor chip including integrated circuit including at least five gate level conductive structures having particular spatial and electrical relationship and method for manufacturing the same | Michael C. Smayling | 2016-08-23 |
| 9425272 | Semiconductor chip including integrated circuit including four transistors of first transistor type and four transistors of second transistor type with electrical connections between various transistors and methods for manufacturing the same | Michael C. Smayling | 2016-08-23 |
| 9425145 | Oversized contacts and vias in layout defined by linearly constrained topology | — | 2016-08-23 |
| 9390215 | Methods for multi-wire routing and apparatus implementing same | Daryl Fox | 2016-07-12 |
| 9336344 | Coarse grid design methods and structures | Michael C. Smayling | 2016-05-10 |
| 9269702 | Methods for cell boundary encroachment and layouts implementing the same | Jonathan R. Quandt, Dhrumil Gandhi | 2016-02-23 |
| D748573 | Solar device charging unit | David Matusich, Michael Becker | 2016-02-02 |
| D748572 | Solar device charging unit | David Matusich, Michael Becker | 2016-02-02 |
| 9245081 | Semiconductor chip including digital logic circuit including at least nine linear-shaped conductive structures collectively forming gate electrodes of at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods | Jim Mali, Carole Lambert | 2016-01-26 |
| 9240413 | Methods, structures, and designs for self-aligning local interconnects used in integrated circuits | Michael C. Smayling | 2016-01-19 |
| 9230910 | Oversized contacts and vias in layout defined by linearly constrained topology | — | 2016-01-05 |