Issued Patents 2016
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9508615 | Clock tree synthesis for low cost pre-bond testing of 3D integrated circuits | Sung Kyu Lim, Pratyush Kamal, Yang Du | 2016-11-29 |
| 9483598 | Intellectual property block design with folded blocks and duplicated pins for 3D integrated circuits | Sung Kyu Lim, Yang Du | 2016-11-01 |